@article{Misc:ITA,
   Author = {Seevinck, E. and van Beers, P. J. and Ontrop, H.},
   Title = {{Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's}},
   Journal = {IEEE Journal of Solid-State Circuits},
   Volume = {26},
   Number = {4},
   Pages = {525-536},
   Year = {1991}
}


@inproceedings{Misc:ISSCC09:Moon,
   Author = {Moon, Yongsam and Cho, Yong-Ho and Lee, Hyun-Bae and Jeong, Byung-Hoon and Hyun, Seok-Hun and others },
   Title = {{1.2V 1.6Gb/s 56nm 6F}$^2${ 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture}},
   Booktitle = {Proceedings of the International Solid-State Circuits Conference},
   Pages = {128-129},
   Year = {2009}
}

@article{Arch:SSA,
   Author = {Udipi, Aniruddha N. and Muralimanohar, Naveen and Chatterjee, Niladrish and Balasubramonian, Rajeev and others},
   Title = {{Rethinking DRAM design and organization for energy-constrained multi-cores}},
   Journal = {ACM SIGARCH Computer Architecture News},
   Volume = {38},
   Number = {3},
   Year = {2010},
   Pages = {175-186}
}

@book{EDA:LogicalEffort,
   author = {Sutherland, Ivan Edward and Sproull, Robert F. and Harris, David F.},
   title = {{Logical effort: designing fast CMOS circuits}},
   publisher = {Morgan Kaufmann},
   year = {1999}
}

@inproceedings{EDA:TransFold,
   author = {Yoshida, H. and Kaushik, De and Boppana, V.},
   title = {{Accurate pre-layout estimation of standard cell characteristics}},
   booktitle = {Proceedings of the 41st Design Automation Conference},
   pages = {208-211},
   year = {2004}
}

@misc{ITRS,
    Author = {{International Technology Roadmap for Semiconductors}},
    Title = {{Process Integration, Devices, and Structures 2010 Update}},
    Note = {\url{http://www.itrs.net/}}
}

@techreport{Horowitz,
 author = {Horowitz, Mark A.},
 title = {Timing Models for {MOS} Circuits},
 year = {1983},
 Institution = {Stanford University}
} 

@inproceedings{NAND:MICRO09:Grupp,
   author = {Grupp, L. M. and Caulfield, A. M. and Coburn, J. and others },
   title = {Characterizing flash memory: Anomalies, observations, and applications},
   booktitle = {Proceedings of the International Symposium on Microarchitecture},
   pages = {24-33},
   year = {2009}
}

@inproceedings{NAND:ISSCC09:Ishida,
   author = {Ishida, K. and Yasufuku, T. and Miyamoto, S. and Nakai, H. and others },
   title = {A {1.8V} {30nJ} adaptive program-voltage ({20V}) generator for {3D}-integrated {NAND} flash {SSD}},
   booktitle = {Proceedings of the IEEE International Solid-State Circuits Conference},
   pages = {238-239,239a},
   year = {2009}
}

@inproceedings{DRAM:6F2, 
   author={Fishburn, F. and Busch, B. and Dale, J. and Hwang, D. and others},
   booktitle={Proceedings of the Symposium on VLSI Technology},
   title={A 78nm {6F}$^2$ {DRAM} technology for multigigabit densities},
   year={2004},
   pages={28-29}
}